When Moore's Law Ends

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        • Computer Architecture with RISC-V Examples
        • Introduction of RISC-V Open ISA
        • Privileged Architecture
        • Schedule
        • Uncore
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      • ARMv8 Architecture
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      • Working with Device Tree (DOULOS)
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      • Case Study Clock Divider with Synchronous Reset
      • FPGA Solution for LiDAR Project
      • Case Study Glitch Free Clock Mux
      • GENUS Training Notes
      • Case Study Clock Skew Control
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      • Register-based SRAM Read Circuit RTL Example using generate
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      • Scan Chain Problem of Clock Generator Flip-Flops
      • My experience with custom digital design
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      • Chisel3 Systolic Array Generator
      • Hardware Security
      • RISC-V Summit 2018
      • SNUG Silicon Valley 2017 at Santa Clara Conventional Center
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      • Observation of IC Industory consolidation of future application
      • Optical Interconnection in Google Data Centers
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      • DAC 2015
      • ISSCC 2015 evening session - Moore's Law challenges below 10nm
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        • Understanding LLaMA2 Part 2 KV Cache
        • Understanding LLaMA2 Part 3 PyTorch Implementation
        • Understanding LLaMA2 Part 4 ExecuTorch Runtime
        • Understanding LLaMA2 Part 5 Training with TinyStories
        • Understanding LLaMA2 Part 6 Positional Encoding
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      • System Performance of Edge AI Applications is Beyond Models
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      • 思考：研究与工程(Thoughts about Research and Engineering)
      • 思考：过度沟通（Over-Communication）
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      • shortcut.py A Command Line Script to Provide Macro
      • Static Site Generator
      • GCP (Google Cloud Platform)
      • Docker for EDA
      • Course Note of Python Design Patterns
      • Scala First Look
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      • Python and Freemind ElementTree
      • A simple system metric collector
      • Ceph on Raspberry Pi (1) Create Storage Cluster
      • Ceph on Raspberry Pi (2) Create Block Device
      • Monorepo vs. Microrepo (ByteByteGo)
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    When Moore’s Law Ends#

    Notes on chip design, computer architecture, machine learning, work, and life.

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