RISC-V Architecture Training

List of training content# [RISC-V Architecture Training] Schedule [RISC-V Architecture Training] Introduction of RISC-V Open ISA [RISC-V Architecture Training] Basics & Unprivileged Specification [RISC-V Architecture …

– Uncore# CPU core is fun, but uncore is the real work.# Uncore / components# Cache (already discussed) Interrupt controller Network Fabric Debug Interrupt recap# 3 types of interrupts External: peripheral devices …

Momentum: 2018 RISC-V Summit# Fun moment: anti-RISCV website by ARM# Schedule# 2-day x 8-hour# Step-by-step# Lecture + demo + DIY# Schedule / Day 1 morning# Schedule and self-introduction Introduction of RISC-V open ISA …

Privileged architecture# Purpose of privileged architecture# To manage and protect shared resources Memory, IO devices, even cores Also needs to decouple implementation details Handle unimplemented operations: software …

What is ISA?# Contract between software and hardware.# What is RISC?# Reduced instruction set computer# Small set of simple/general instructions + load/store architecture Optimize hardware to be simple and faster …

Computer architecture basics# Pipeline / Parallelism / Cache# Three ultimate mechanisms to imporve performance/power Computer architecture basics / pipeline# IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, …

RISC-V SPEC# https://riscv.org/specifications (official version v1.10) https://github.com/riscv/riscv-isa-manual (source code) User-level ISA (unpriviledged)# All the basic instructions, and extensions Memory model …