RISC-V Architecture Training on When Moore's Law Ends

Dec. 2019 verion Full List

Thu, 28 Nov 2019 00:00:00 +0000

List of training content#

Basics & Unprivileged Specification

Wed, 27 Nov 2019 00:00:00 +0000

RISC-V SPEC#

https://riscv.org/specifications (official version v1.10)

https://github.com/riscv/riscv-isa-manual (source code)

User-level ISA (unpriviledged)#

All the basic instructions, and extensions
Memory model

Priviledged ISA#

Priviledge level: M (machine), H (hypervisor), S (supervisor), U (user)
CSR (control status register)
Virtual-memory system

Debug & Trace#

First impression: ISA subsets#

RISC-V is a family of ISAs#

Divided into several subsets: I, M, A, F, D, C, …

Domain-specific architecture (by David Patterson)
- The ending of Moore’s Law => domain-specific architecture is the future of computing
- Too costy to be “general purpose” anymore
  - Too many new domains
  - Not enough transistors or power to be general purpose
- E.g. TPU-like xPU for AI computing
RISC-V ISA’s approach

Computer Architecture with RISC-V Examples

Wed, 27 Nov 2019 00:00:00 +0000

Computer architecture basics#

Pipeline / Parallelism / Cache#

Three ultimate mechanisms to imporve performance/power

Computer architecture basics / pipeline#

IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back).

Computer architecture basics / pipeline#

@DEMO#

Pipeline simulator: https://github.com/mortbopet/Ripes

Computer architecture basics / pipeline#

Motivation#

Most of the work cannot be done at the same time.
To use the logic more efficiently
Less work per stage, higher clock frequency

Brings in problems: hazards#

Data hazard
- Dependency

mv	x1, x2
add	x4, x1, x3
sd	x4, 0(x5)

Control hazard
- Jump and branch

addi	x1, x1, 1
subi	x2, x1, 100
bnez	x2, 0(x3)

.co-4[

Introduction of RISC-V Open ISA

Wed, 27 Nov 2019 00:00:00 +0000

What is ISA?#

Contract between software and hardware.#

What is RISC?#

Reduced instruction set computer#

Small set of simple/general instructions + load/store architecture
- Optimize hardware to be simple and faster
- Software-centric design: rely on compiler + software

CISC	RISC
Emphasis on hardware	Emphasis on software
Includes multi-clock complex instructions	Single-clock, reduced instruction only
Memory-to-memory: “LOAD” and “STORE” incorporated in instructions	Register to register: “LOAD” and “STORE” are independent instructions
Small code sizes, high cycles per second	Low cycles per second, large code sizes
Transistors used for storing complex instructions	Spends more transistors on memory registers

E.g. Alpha (DEC), SPARC (SUN), MIPS (now Wave), Power (IBM), ARM

What is RISC?#

John Hennessy & David Patterson
- Authers of computer architecture bible “Computer Architecture: A Quantitative Approach” (for graduates)
- Also “Computer Organization and Design” (for undergraduates)
- Turing Award 2017

Privileged Architecture

Wed, 27 Nov 2019 00:00:00 +0000

Privileged architecture#

Purpose of privileged architecture#

To manage and protect shared resources
- Memory, IO devices, even cores
Also needs to decouple implementation details
- Handle unimplemented operations: software emulation
- Handle async events (interrupts): IO, timer, software
- Hypervisor support: 2-level address translation

Therefore, we have#

4 privilege modes: U, S, H, M
PMP/PMA (physical memory protection/attributes)
Virtual memory
Interrupts and exceptions
And a bunch of CSRs to serve these functionality

Privileged architecture / software stack layers#

4 different kinds of platforms#

Platforms	Modes	Trust	Memory protection
Embedded w/o protection (most MCUs)	M	All	Non
Embedded w/ protection (RTOS scenario)	M+U	Application	Physical memory protection
OS capable (Linux, and etc.)	M+S+U	OS	Virtual memory
Cloud OS capable (multiple OS running on the same hardware)	M+H+S+U	Hypervisor	2 level of virtual memory

Privileged architecture / software stack layers#

Schedule

Wed, 27 Nov 2019 00:00:00 +0000

Momentum: 2018 RISC-V Summit#

Fun moment: anti-RISCV website by ARM#

Schedule#

2-day x 8-hour#

Step-by-step#

Lecture + demo + DIY#

Schedule / Day 1 morning#

Schedule and self-introduction
Introduction of RISC-V open ISA
- History and current status of ecosystem
RISC-V ISA: unprivileged spec
- Basic RISC-V ISA: key concepts
DIY 0: setup course DIY env
- Quick introduction of DIY env used in this course
Lunch break

Schedule / Day 1 afternnon#

Demo 1: compile assembly code and simulate on SPIKE

Uncore

Wed, 27 Nov 2019 00:00:00 +0000

–

Uncore#

CPU core is fun, but uncore is the real work.#

Uncore / components#

Cache (already discussed)
Interrupt controller
Network Fabric
Debug

Interrupt recap#

3 types of interrupts

External: peripheral devices
Software: inter-processor interrupt
Timer: timely schedule tasks

PLIC (platform level interrupt controller)#

For external interrupts
Aggregation of multiple external interrupts
- Provide enable/priority

CLINT (core level interruptor)#

For software & timer interrupts
Provide memory-mapped software/timer interrupt CSRs

PLIC (platform-level interrupt controller)#

MSI vs. IRQ#

MSI (message signaled interrupt)	IRQ (physical wired interrupt)
Relatively newer	Traditional and easy to understand
More complex device and interrupt controller	Simple to implement. Widely supported
Scalable, especially for morden large SoCs	Don’t scale well
In-band access, easy for timing/clock/etc.	Out-of-band, nightmare for physical design if many

Interrupt controller for RISC-V: PLIC#

Simple & easy to use
IRQ-style interrupt aggregator
Support programmable priority and enable
Support multiple source and multiple target

PLIC / function diagram#

IRQ-style interrupt aggregator that support enable/priority and claim/complete flow