Schedule

November 27, 2019

Momentum: 2018 RISC-V Summit#

Schedule and self-introduction
Introduction of RISC-V open ISA
- History and current status of ecosystem
RISC-V ISA: unprivileged spec
- Basic RISC-V ISA: key concepts
DIY 0: setup course DIY env
- Quick introduction of DIY env used in this course
Lunch break

Demo 1: compile assembly code and simulate on SPIKE
- GNU toolchain, assembly code example, compile & link, SPIKE simulator
DIY 1: compile assembly code and simulate on SPIKE
- Code your own assembly code, compile & link, run simulation on SPIKE
Tea break
RISC-V ISA: privileged spec
- Privilege modes, exception & interrupt, physical memory & virtual memory
Demo 2: C code with proxy kernel and front-end server
- RISC-V sim env components, system call workflow, use PK to run “hello world” in SPIKE
DIY 2: create new system call
- Change FESVR and PK to add a new system call, write C code to call this system call

CPU architecture with RISC-V examples
- Basic concepts of CPU architecture, and some real RISC-V CPU examples
Demo 3: verification suite
- ISA tests and built-in-self-check, Torture: random code generator
Demo 4: RocketChip generator
- CPU architecture exploration with RocketChip generator
DIY 4: generate new CPU with RocketChip
- Configure RocketChip in Chisel to generator new CPU, and run benchmark
Lunch break

Demo 5: Freedom IDE & HiFive1 board
- Quick example of SiFive’s Freedom IDE, and debugging HiFive dev board
Uncore components
- TileLink, PLIC, CLINT, CLIC, debug, trace
Demo 6: create custom instruction
- Select instruction encoding, change GCC to support new instruction
Tea break
Demo 7: QEMU full system emulator
- Boot linux in QEMU
- Linux binary vs. newlib binary
Vector extension (backup)
- RISC-V’s answer to machine-learning

本科：清华大学电子工程系

博士：中科院计算所龙芯

工作：

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