Chip Design

Intro# Device tree: for non-discoverable hardware, included in BSP Source type Old style: C code BSP, files compiled into the kernel New style: device-tree BSP -> device tree blob (load by boot loader) Compilation# …

// Some simple example #include <systemc.h> SC_MODULE (seq_and2 ) { // sequential AND2 sc_in< sc_uint<8> > a; sc_in< sc_unit<8> > b; sc_out< sc_uint<8> > f; sc_in<bool> …

When using a counter to divide a clock, don’t reset the counter, especially when you are using synchronous reset. It will make the clock quiet while reset. And if it’s used along with sync reset, then those flip-flop …

1-stop solution: Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit (https://www.xilinx.com/products/boards-and-kits/zcu111.html) Features: XCZU28DR-2FFVG1517E: high-end RFSoC 12-bit 4GSPS ADC x8, 14-bit 6.5GSPS DAC x8 (all …

If your design needs to switch from one clock source to another, there is high possibility of harmful clock glitches while switching. Normally you need to stop this clock during the switching process, but what if you …

The following is my notes of GENUS training course on Cadence’s training module Module 03: genus fundamentals# common UI vs legacy mode# unified commands with Tempus common us: set_db & get_db legacy mode: …

Question: how to control the clock skew between a group of clocks to be minimum, say less than 30ps, instead of utilizing useful skew? This case happens to our hard macros. A: in Innovus, use skew group set …

The following is my notes of INNOVUS training course on Cadence’s training module Module 02: overview# “gift” directory contains lots of useful scripts to help productivity Independent “viewlog” utility or …

Some parameterized example RTL code for register-based SRAM read circuit using “generate” feature parameter d = 32; // FIFO depth parameter w = 64; // FIFO data bit-width logic [w-1:0] mem [d-1:0]; // FIFO memory array …

This is my reading note of book “SystemVerilog for Design (2nd edition)". As a non-full-time RTL designer, it has opened my mind. But still, I’m sad about the antient tool that we are using to design …

As shown in the schematic, we have some clock divider that divide root clock by half. While in scan mode, these flip-flops will be bypassed and treated as normal flip-flop that need to be inserted into the scan chain …

Background# This is the summary of my experience from project LBRAM in Marvell in the year of 2014. The first thing: discuss timing/area/power SPEC’s in details# Most of the time, because custom design takes lots of …

从2017年初的观点来看，这篇报告的部分内容过时了，但是整体结构还是比较适合的。希望今年有时间能够出一版更新的版本。 低功耗设计的最根本驱动力是集成电路芯片的功耗随着工艺的进步不仅没有下降反而不断上涨。因为晶体管速度和集成度的上升速度超过了电路单次翻转所消耗能量的下降速度，所以单位面积芯片的功耗在迅速上升。而根据ITRS的预测，固定电源供电设备和移动设备中芯片的功耗发展趋势如图表 1所示。从中我们不难看出，各类芯片的各种功耗都在不断飞 …

#hardware #accelerator #chisel #open-source I’ve tried to learn Chisel 5 years ago, but gave up and went back to SystemVerilog to design our RISC-V CPU + AI custom instructions from scratch. After 5 years, both …