Chip Design on When Moore's Law Ends

Working with Device Tree (DOULOS)

Mon, 21 Jan 2019 00:00:00 +0000

Intro#

Device tree: for non-discoverable hardware, included in BSP
Source type
- Old style: C code BSP, files compiled into the kernel
- New style: device-tree BSP -> device tree blob (load by boot loader)

Compilation#

In-tree vs. out-of-tree

dtc command

convert .dts to .dtb, and backwards

Device tree syntax#

devicetree.org
Nodes
Properties
- Values
Root node = /
Values format
- int, string, list of string, phandle (reference to other node)
Standard properties

SystemC Tutorial

Fri, 07 Dec 2018 00:00:00 +0000

// Some simple example

#include <systemc.h>

SC_MODULE (seq_and2 ) { // sequential AND2
 sc_in< sc_uint<8> >		a;
 sc_in< sc_unit<8> >		b;
 sc_out< sc_uint<8> >	f;
 sc_in<bool>				clk;

 void func() {
 f.write( a.read() & b.read() );
 }

 SC_CTOR ( seq_and2 ) {
 SC_CTHREAD(func);
 sensitive << clk.neg();
 }
}

Port & signal#

Port
- sc_in & sc_out
- .read() & .write() functions
Signal
- sc_signal

Threads#

SC_METHOD()
- Just like always_comb in Verilog, but you have to list the sensitive list
SC_THREAD()
- Not commonly used
- Behavior like initial in Verilog
SC_CTHREAD(function name, clock sensitive)
- Most commonly used
- Only sensitive to clock edge, just like always_ff in Verilog
- Not limited to one cycle
sensitive keyword to define the sensitive list

Datatypes#

Integers

Case Study Clock Divider with Synchronous Reset

Thu, 25 Oct 2018 00:00:00 +0000

When using a counter to divide a clock, don’t reset the counter, especially when you are using synchronous reset. It will make the clock quiet while reset. And if it’s used along with sync reset, then those flip-flop won’t be reset at all.

But if without reset, the counter will be “X” in simulation.

logic [1:0] cntr;

`ifndef SYNTHESIS
initial begin
 cntr = 2'b00;
end
`endif

always_ff @ (posedge clk) begin
	cntr <= cntr + 1;
end

FPGA Solution for LiDAR Project

Tue, 23 Oct 2018 00:00:00 +0000

1-stop solution: Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit (https://www.xilinx.com/products/boards-and-kits/zcu111.html)
- Features:
  - XCZU28DR-2FFVG1517E: high-end RFSoC
  - 12-bit 4GSPS ADC x8, 14-bit 6.5GSPS DAC x8 (all RFSoC has the same type of ADC/DAC, no higher speed ones)
- Pros: 1-stop with everything we need for bench-top demo
- Cons: expensive $9K, need secondary solution for backup; overkill for second step product
FMC daughter board with high-speed ADC
- FMC163 (https://www.abaco.com/products/fmc163-fpga-mezzanine-card)
  - 1x 12-bit ADC, 4.0 GSPS at single channel, or 2GSPS at dual channel, LVDS (TI’s ADC12D2000RF)
  - 1x 14-bit DAC, 5.7 GSPS, LVDS (ADI’s AD9129)
  - Question: will it work with our backup dev boards?
- AD-FMCDAQ2-EBZ (https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcdaq2-ebz.html)
  - 2x 14-bit ADC, 1.0 GSPS, JESD204B (ADI’s AD9680)
  - 4x 16-bit DAC, 2.8 GSPS, JESD204B (ADI’s AD9144)
  - $1495, buy directly from ADI
- EVAL-FMCDAQ3-EBZ (https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-fmcdaq3-ebz.html)
  - 2x 14-bit ADC, 1.25 GSPS, JESD204B (ADI’s AD9680)
    - Question: why the same device, here is 1.25G but it’s 1.0G previously
  - 2x 16-bit DAC, 2.5 GSPS, JESD204B (ADI’s AD9152)
  - $1495, buy directly from ADI
    - ADI provides the whole package, including RTL for FPGA, dev board schematic and etc.
- ADC12D1800RF Reference board (http://www.ti.com/tool/ADC12D1800RFRB?keyMatch=adc12d1800rfrb)
  - 12-bit, dual 1.8 GSPS or single 3.6 GSPS, LVDS (TI’s ADC12D1800RF)
  - $2999, buy directly from TI
  - It has a Xilinx Virtex-? on board, but I doubt it can be programmed

Case Study Glitch Free Clock Mux

Sat, 31 Mar 2018 00:00:00 +0000

If your design needs to switch from one clock source to another, there is high possibility of harmful clock glitches while switching. Normally you need to stop this clock during the switching process, but what if you design relies on non-stop clock? Here is the circuit proven to work on silicon.

Techniques to make clock switching glitch free

We used it in our 28nm TSMC HPC+ chip, after we carefully simulated it with HSPICE. If possible, make it a hard macro. But if you cannot do that, ask the back-end engineers to

GENUS Training Notes

Fri, 05 May 2017 00:00:00 +0000

The following is my notes of GENUS training course on Cadence’s training module

Module 03: genus fundamentals#

common UI vs legacy mode#

unified commands with Tempus
common us: set_db & get_db
legacy mode: set_attribute & get_attribute
- .synth_init file: setup info, auto load when start legacy UI, can be skipped with -no_custom command line option

explore design hier in legacy UI#

virtual directory structure
- /: root dir
  - designs
    - top_module
      - instances_hier: current module’s hier instances
      - instances_seq: current module’s sequential instances
      - instances_cmb: current module’s combinational instancs
  - libraries
  - hdl_libraries
  - flows
- use find to locate objects
  - ex. find all the pins find /designs/* -pin *
- use ls + cd to navigate through this virtual directory structure
  - even rm, mv, pushd, popd
  - report all related attributes associated for all the pins: ls -la [find /designs/* -pin *]
navigate UNIX disk
- lpwd, lcd, lls

attributes#

set_attribute <attr_name> <value> <object>
get_attribute <attr_name> <object>
- works on single object only
get help
- get_attribute -h <attr_name> [<object_type>]
  - get help on attribute
  - <attr_name> can include wildcards
- set_attribute -h: reports writable attr
attr are dependent on the stage of synthesis flow

input and output#

input: RTL + constraint + library + power intent + physical
output: netlist + LEC dofile + ATPG, scanDEF + constraints + physical design input files

template script#

write_template

flow#

setup libraries

set_attribute init_lib_search_path <path> /
set_attribute library $ls_lib
library domain for low-power design (if not included in CPF)
- create_library_domain {lib_domain1 lib_domain2}
- set_attribute library $ls_lib1 lib_domain1 power_domain1
dont use
- set_attribute avoid <1/0> <cell_names>
- or use set_dont_use <cell_names>
(optional) setup physical layout estimation (PLE)
- dynamically calculates wire delays for different logic structures
- vs Genus-Physical
  - floorplan DEF is optional
- set_attribute lef_library <lef_header>
- set_attribute qrc_tech_file <qrc_tech_file_path>
- set_attribute interconnect_mode ple

read HDL

set_attr init_hdl_search_path <path> /
read_hdl

elaborate

what
- build data structure, infer registers
- high-level HDL opt, remove dead code
- identify clock gating candidates
- overwrite parameters for diff modules
elaborate
- after elaboration, the /designs is populated
check_design -all
- must: unresolved references

read constraints

read_sdc (preferred)
echo $::dc::sdc_failed_commands > failed.sdc
check_timing_intent -verbose
- check failed commands and errors

opt directives

preserve instances and subdesign (dont touch)
- set_attr preserve <option> (more options than set_dont_touch)
  - false/true
  - delete_ok
  - const_prop_delete_ok
  - const_prop_size_delete_ok
  - size_ok
  - map_size_ok
  - size_delete_ok
grouping/ungrouping hierarchy
- group -group_name <name> <ls_inst>
- ungroup <hier>
- disable ungrouping by set_attr ungroup_ok false <inst>
boundary opt (default performed)
- disable by set_attr boundary_opto false <sub_design>
- use dynamic hierarchical check to verify boundary opt in conformal LEC
opt sequential logic (default performed)
- remove unused flops that is not driving an output port
- disable by
  - set_attr hdl_preserve_unused_register true /
  - set_attr delete_unloaded_seqs false /
  - set_attr optimize_constant_0_flops false /
  - set_attr optimize_constant_1_flops false /
- same thing to combinational logic that drives unloaded hier pins
  - disable by set_attr prune_unused_logic false <pins>
merge sequential logic (default performed)
- combine flops and latches that are equivalent in the same hierarchy
- disable by
  - set_attr optimize_merge_flops false /
  - set_attr optimize_merge_latches false /
  - set_attr optimize_merge_seq false <inst>
multibit cell inference (MBCI)
- flops/tri-state cell/MUX/inverters/…
- share clock to reduce power/improve reliability
- LEC support
- can control naming style (for verification)
- set_attr use_multibit_cells true
other opt
- opt async reset logic
  - set_attr time_recovery_arcs true /
- auto ungrouping
  - set_attr auto_ungroup {none | both}
- keep the synchronous feedback logic immediately in front of the sequential elements (?)
  - set_attr hdl_ff_keep_feedback
  - affect how enable logic of a flop is implemented
- opt TNS other than WNS
  - set_attr tns_opto true /

synthesis

1st level: syn_generic <-physical>
- tech independent RTL opt
  - can skip for netlist-to-netlist synthesis
- set_attr syn_generic_effort
  - medium by default
2nd level: syn_map <-physical>
- mapping to lib, and logic opt
  - initial structuring
    - constant propagation, clock gating
    - structuring for best delay
  - target info
    - estimate timing
  - global mapping
    - mapping to meet target
  - global incremental
    - net/drive opt
    - timing tuning
- set_attr syn_map_effort
  - high by default
- check the slack, if too negative, check the constraint/design
3rd level: syn_opt <-physical> <-spatial> <-incr>
- opt gates
  - fix drc, cleanup area, cleanup timing
- set_attr syn_opt_effort
  - high by default
global effort
- set_attr syn_global_effort
- set to express while explore flow
  - accept not clean design

analyze and report

after elaboration
- check_design unresolved
constraint
- check_timing_intent
- use Conformal Constraint Designer (CCD) tool to validate timing constraint
  - write_to_ccd validate -sdc > dofile generate dofile used in CCD
check preserve attributes, remove those that are not needed
ungrouping small blocks can improve timing/area
reports
- report_area
- report_dp (datapath)
- report_design_rules (drc)
- report_messages
- report_power
- report_qor
- report_timing
- report_summary
from GUI
- timing -> timing lint: gives a thorough

gen outputs

write_hdl > filename
write_sdc > filename
write_design -innovus

command help#

setenv MANPATH $CDN_SYNTH_ROOT/share/synth/man to view man pages from UNIX shell

Module 04: datapath#

datapath info in virtual file system#

/hdl_libraries/
- /hdl_libraries/CW (chipware)
- /hdl_libraries/DW (designware)

datapath operation#

architecture selection
sharing and speculation (unsharing)
carry-save arithmetic (CSA)
…

datapath directives#

CSA
- set_attr dp_csa {inherited|basic|none} <design>
sharing and speculation
- sharing: improve area
- set_attr dp_sharing
- set_attr dp_speculation
arch selection
- manually control datapath arch selection (not recommended)
  - set_attr user_speed_grade [find /designs* -subdesign <name>] while speed can be ver_fast|fast|medium|slow|very_slow
reordering (reorder input to opt critical path)
ChipWare (CW)
- also maps DesignWare components in RTL to CW

opt in syn_generic#

constant propagation
resource sharing
logic speculation
MUX opt
CSA opt
datapath rewriting
- QoR driven RTL code rewrite
- by default during syn_generic with high effort level
- no LEC impact
- ex.

assign p = a - b;
assign q = a + b;
assign y = s ? p : q;

# better timing, smaller area
assign t = {16{s}} ^ b;
assign y = a + t + s;

report#

set_attr hdl_track_filename_row_col true / before read_hdl
report_dp after every stages: elaboration/syn_gen/syn_map/syn_opt to track datapath components changes

Module 05: debug design scenarios#

problem with sdc#

check the log file for errors and warnings
check constraint consistency by check_timing_intent -verbose before synthesis

path grouping#

cost group: opt cost groups simultaneously according to their weight, to minimize their WNS for each group
path group -> cost group

tighten/relax constraint#

emphasize some paths in opt without impacting output SDC
path_adjust -from <obj> -to <obj> -delay <delta_slack_ps>
- if delta_slack_ps < 0, tighten the path
- if delta_slack_ps > 0, loosen the path
use rm [find /des* -exceptions pa_*] before report timing to get normal timing reports
- the adjustment will be in the timing report if not removed

bottom-up design flow#

promote submodule
- create_derived_design promote submodule to top-level module

Module 06: physical synthesis#

why?#

for synthesis: all wires of fanout=n are the same
for physical: each wire is unique
- 80% to 90% of wires are local, the rest are big problems
old tricks don’t work: over-constraint

how?#

incremental congestion prevetion
structural datapath
physical aware clock gating/logic structuring/mapping
use floorplan as bridge to close pre and post layout gap
- def file: must define die size; macro locations, fences/guides/regions are better to have (impact timing)
genus vs innovus: 5% timing & wirelength diff

spatial flow#

if backend is going to run full place_opt, instead of place_opt -incr with genus-physical outputs as inputs, then no need to waste time on the final syn_opt stage
use syn_opt -spatial instead of syn_opt -physical

PAM (physical-aware mapping) & PAS (physical-aware structuring)#

automatically turned on with -physical

useful attributes#

invs_enable_useful_skew
phys_ignore_nets
pqos_ignore_msv
- whether to pass lib or power domain info to INVS
invs_user_constraint_file
- sourced during INVS session
- invs_preload_script & invs_postload_script & invs_preexport_script
number_of_routing_layers
- important to have
invs_pre_place_opt
pqos_placement_effort
- congestion effort
invs_gzip_interface_file
invs_temp_dir

correlation between genus-phys and invs#

ensure NDR and layer-promotion info is passed to innvous
assure wirelength has good correlation

early stage physical analysis#

at generic physical synthesis stage
why?
- analyze hier
- hard macro locations
- floor plan constraints
- timing debug with gui

check placement legality#

check_placement

edit floorplan in Genus GUI#

go into edit mode

report#

write_report
- wrote QoS statistics
report_summary
- write summary table
write_snapshot
- design database and reports

FAQ#

recommended flow
- after synthesis with physical, write_design -innovus
- then in innovus load the output data, and place_opt_design -incr
what is under the hood of syn_opt -phy?
- it calls place_opt -phy_syn in INVS, and load back the result and do low effort TNS/WNS opt
- so the engine is the same between genus-phy and invs
is it possible to do CTS in genus?
- No. but simple CTS will be enabled in coming versions

debug with common ui#

timing debug
- timing -> debug timing
- diff path groups histogram
- highlight violating path

Module 07: low power opt#

low power opt impacts timing a lot
- trade-off

flow#

enable clock gating
annotate switching activities with TCF/SAIF/VCD
apply clock-gating directives
apply leakage/dynamic power constraints
synthesis with clock gating insertion/power opt
analyze

multi-Vth lib#

low VT on timing critical path, high VT on non-critical path

clock gating#

set attr lp_insert_clock_taing true /
specify clock gating cell
- customied: lp_clock_gating_module attr
- select from library: lp_clock_gating_cell attr
disable clock gating: lp_clock_gating_exclude
control fanout of CGC: lp_clock_gating_*_flops
common enable: lp_clock_gating_extract_common_enable
clock gating for sync reset

backannotate switching activity#

read_tcf (toggle count format)
read_saif (converted to TCF internally)
read_vcd
manipulate activity with lp_toggle_* attr

Joules: RTL power estimation#

effort#

leakage_power_effort attr
- {none | low | high}
disable leakage power opt
- max_leakage_power must not be set while leakge_power_effort set to none
dynamic vs leakage
- lp_power_optimization_weight attr: power = weight * leakage + (1 - weight) * dynamic
  - normally, weight is close to 1
- POPT-501

report#

report_clock_gating
report_power
get power-related info
- lp_internal/leakage/net_power
- lp_default_toggle_rate
- lp_default_probability

useful attr#

lp_clock_gating_exceptions_aware
declone/share/split/merge_clock_gate

Module 08: design for test#

flow#

setup DFT rule, and check
- shift enable
- test mode
- prevent scan mapping of flops
- internal clock as test clock
- DFT controllable constraints
- abstract scan segment
add test logic
- insert test point
- insert shadow logic
synthesis
setup DFT config, and preview scan chains
- scan chain: number, length
- control data lockup elements
connect scan chains
incremental opt

DFT in virtual file structure#

/designs/dft

DFT constraint#

2 scan styles: controlled by dft_scan_style attr

muxed style (muxed_scan) (most commonly used)
clocked LSSD (clocked_lssd_scan) (1 system clock, and 2 scan clocks)

define shift enable signal
- for muxed style: define_shift_enable
  - default one for common usage, or each chain has its own enable signal
- for LSSD style: define_lssd_scan_clock_a/b
define test mode signal: define_test_mode
- put circuit in test mode so that gated clocks are all activated
define test clock domains: define_test_clock -name <name> -domain <domain> <pin_name>
- due to unbalanced clock tree, create separate test clock domains to prevent timing issues
- lock-up latches (auto added) for crossing test clocks in the same domain, if more than 1 test clocks are defined in one domain
- by default, in the same test clock domain use the same clock edge (controlled by dft_mix_clock_edges_in_scan_chain attr)
define scan segment
- define_scan_abstract/fixed/floating/preserved_segment
- define_scan_shift_register_segment
- define_jtag_boundary_scan_segment
preserve nonscan flops
- set dft_scan_map_mode attr to preserve
- set dft_dont_scan attr to true
control the length and number
- by default, no max length for scan chain
- dft_min_number_of_scan_chains
- dft_max_length_of_scan_chains

DFT rule check#

uncontrollable clock nets
uncontrollable async set/reset nets
conflicting clock and async set/reset net
shift register rules
abstract segment rules
check_dft_rules
fix_dft_violations (only for muxed style)
check_atpg_rules
- only generate script for Modus ATPG rule checker
check_design
analyze_atpg_testability
- run Modus

add DFT logic#

insert_dft *
identify shift register to save area (auto done)
- cmd = identify_shift_register_scan_segments
mapping to scan in a already mapped netlist
- set_scan_equivalent: one-to-one correspondence between non-scan and scan flop lib cells
- replace_scan

connect scan chains#

connect_scan_chains

report and output#

report_scan_chains
report_scan_setup
write_scandef
write_dft_atpg*: interface to ATPG tool
write_dft_abstract_model

bottom-up scan flow#

block level
- create block level chains
- write_hdl -abstract
- write_dft_abstract_model
top level
- read_dft_abstract_model
- connect_scan_chains

Module 09: LEC#

guidance to address formal verification challenge#

challenges
- datapath arch
- ungrouping: no manual random ungrouping
- boundary opt
- phase inversion
long run-time, werid mismatch

recommended 2-step verification#

1st-step: synthesis with preserved datapath modules/hier, restrict certain opt, min ungrouping, and output intermediate gate netlist
2nd-step: incremental synthesis with additional opt and ungrouping, and output final gate netlist
compare: RTL vs intermediate netlist, then intermediate netlist vs final netlist

cmd#

write_lec_script -revised_design inter.v
write_lec_script -revised_design final.v -golden_design inter.v

attr affects formal verification#

datapath: dp_*
boundary opt
ungrouping
retime
wlec_*

in LEC#

analyze datapath: to analyze datapath modules
analyze abort -compare -thread 4: multithreading abort resolving
module-level datapath analysis (MDP)
- improve quality
- analyze datapath -module xxx

Module 10: interface#

netlist#

possible modifications
- bit blasted port/constants
  - set_attr write_vlog_bit_blast_mapped_ports true / and set_attr bit_blasted_port_style %s_%d /
- name changing: update_names cmd
- loop breaker: break comb feedback loops
- remove assign statement (not needed in INVS)
  - set_attr remove_assigns true /

Appendix#

retiming#

set_attr retime true [find / -subd xxx]
retime -prepare -min_delay -effort high [find / -subd xxx] before syn_gen

advanced low-power flow#

CPF
MSMV

common ui#

attr
- set attr: set_db <attr_name> <value> <object>
- query attr: get_db <attr_name> <object>
- help *clock* -attribute
virtual directory structure
- vcd
- vls
- rename_obj
- vpopd
- vpushd
- delete_obj
- vfind
examples
- find all designs: get_db .designs
- find all comb leaf inst under current directory: get_db . .insts -if .is_comb
- find all inst of a certain cell type: get_db insts -if {.base_cell.name == DFFX1}
- calc leakage power of a hier: expr [join [get_db hinst:CORE/ALU .insts.leakage_power] +]
- fanout histogram

set tot [llength [get_db nets]]
for {set i 0} {$i <= 100} {incr i 5} {
 set n [llength [get_db nets -if ".num_loads>$i && .num_loads<[expr {$i+5}]"]]
 puts [string report "#" [expr $n * 100 / $tot]]
}

- find all pins: `vls -la [vfind /designs/* -pin *]`

MMMC setup flow
- read_mmmc
- read_physical -lef
- read_hdl
- elab
- read_def
- read_power_intent
- init_design -skip_sdc_read
- syn_gen/map/opt

clipper flow#

block level physical synthesis <-> unit level physical synthesis
- unit level cannot understand block level’s congestion and physical context issues
- so pass timing/physical context DEF and constraint from block level to unit level
CMD
- create_clip at higher level
  - block boundary must be preserved (remember, genus is very aggressive about optimizing)
- read_clip at lower level

Advanced Synthesis#

Case Study Clock Skew Control

Tue, 18 Apr 2017 00:00:00 +0000

Question: how to control the clock skew between a group of clocks to be minimum, say less than 30ps, instead of utilizing useful skew? This case happens to our hard macros.

A: in Innovus, use skew group

set min_skew_group {
 path/to/clock/NLVB_CKB
 path/to/clock/NLVA_CKB
 path/to/clock/NLVP_CKB
}

create_ccopt_skew_group \
 -name min_skew_group \
 -sources path/to/clock/source/CKB \
 -sinks $min_skew_group \
 -target_insertion_delay 0.500 \
 -rank 1
 -target_skew 0.000

set_ccopt_property constraints -skew_group min_skew_group ccopt

INNOVUS Training Notes

Sat, 01 Apr 2017 00:00:00 +0000

The following is my notes of INNOVUS training course on Cadence’s training module

Module 02: overview#

“gift” directory contains lots of useful scripts to help productivity
Independent “viewlog” utility or “Tools->Log Viewer” will start a GUI to help understand log files better.
Batch mode: innovus -no_gui -init batch.tcl
- win / win off to show/hide GUI

Module 03: import design#

Input#

Netlist in Verilog
Floorplan in DEF
Clock tree spec auto gen from SDC
Scan info in Tcl or DEF
I/O info (pads or pins)
GDS layer map (if want to dump GDS)
Timing constraint in SDC
Timing library in .lib
LEF library of cells
Tech file for extraction (cap table or qrc)

import design#

Save all the input file paths and parameters in a .globals file, then next time just use source design.globals; init_design.
Q: what if there is errors, such as mismatch between netlist and libraries?
- A: in early stage, mismatch is OK. For example, importing a new Verilog netlist but along with an old DEF containing floorplan. But in late stage, the mismatch is serious.
Tips: save and load a workspace (window layout) use menu “Windows -> Save Workspace”.
Tips: menu could be customized using terminal commands “ui*”

check design#

checkDesign to detect missing/inconsistency
- ex: checkDesign -floorplan -outfile checkDesign.floorplan.rpt
- ex: checkDesign -timingLibrary

design mode#

setDesignMode -process 16 -flowEffort {express|standard|extreme}

Module 04: select and highligh obj#

select#

selectObjByProp <objType> <expression>
F12: dim the background
“instance (right click) -> highlight instance nets”

design browser#

“tools -> design brower”
All design stuff in a tree; can use it to select obj and do placement
Color the modules: right click on “modules”

schematic viewer#

“tools -> schematic viewer”
To explore design changes
Can cross-probe to physical window

three views#

floorplan view
amoeba view : display outline of modules/sub-modules after placement to check locality of the module
physical view: detailed placments and routing

Module 05: floorplan#

sites and rows#

site: basic horizontal unit
row: core rows / IO rows

what is floorplanning?#

define die size
place IO
create soft blocks
power planning
macro placement
early routing congestion/utilization check

specify floorplan#

“floorplan -> specify floorplan” = floorPlan
Leave space between core and IO to place power rings
Tips: evaluate routing resource (number of layers, routing tracks) to decide if the core should be high & thin or short & wide
- core utilization = standard cell + macros / area
- cell utilization = standard cell / area
orientation
- R0: no rotation
- R90: counter-clockwise 90 degree rotation
- MX: mirror through X axis
- MY: mirror through Y axis

assign pads and pins#

either read in DEF file or Innovus IO file format; or randomly create one then dump out and modify
“edge 0” is the left-most edge at Y=0 which is the staring point for IO assignment
“User Guide -> infrastructure -> data preparation -> generating the IO assignment file”

automatic floorplan#

Seed: design blocks definition used to guide the auto floorplan (not a seed for randomization)
Use setPlanDesignMode to control some advanced placement options
use planDesign create init floorplan
NOTE: most of the time, not useful at all

floorplan toolbox#

placement blockage type
- hard: restricted no
- soft: can be used during place opt, CTS, ECO, legalization
- partial: percentage of unavailability
routing blockage: layer / type specific
rectilinear object use scissor tool
rectilinear floorplan
- view -> preference -> enable rectlinear design
“floorplan -> resize” = setResizeFPlanMode / resizeFloorplan
stairway style floorplan edge
relative floorplan: move in a group
- create_relative_floorplan -horizontal_edge_separate {target_edge distance ref_edge} -vertical_edge_separate ...
- delete_relative_floorplan
“floorplan -> edit floorplan” has the same tools with the toolbox to do the job

create row#

“floorplan -> row -> create core row” = createRow
- need to choose the site
rows can be stretched using “floorplan -> row -> stretch core row”
sometimes can create rows outside of core into the pad area

rectilinear blockage#

also use the “cut rectilinear” tool

module constraint types#

5 different levels of module constraint types
1. None
2. soft guide (SoftGuide): weakly grouping instances under the same soft guide, but actually they can be placed through out the whole core area
3. guide (Guide): preplacement guide for the module in the core design area
4. region (Region): force instances in the regsion, but allow other modules in as well
5. Fence (Fence): like region but don’t allow other modules. A module becomes a fence when the module is specified as partition. Usually used for hierarchical (bottom-up) design.
Tips: when first imported design, all std cell instances will be under the same top module, you have to ungroup it to break it down into pieces.
Tips: TU = target utilization (std cell + macro); EU = effective utilization (std cell + macro + blockage)

instance placement status#

change from “placed” to “fixed” after floorplan for macros
softfixed: cannot be moved by global placement, but can be moved by legalization and upsize by optimization

placement halo#

diff from blockage, halo move along with the target block
“floorplan -> edit floorplan -> edit halo” = addHaloToBlock / deleteHaloFromBlock

routing halo#

prevent signal integrity issues around macros
- direct connection is ok
- no long wires
- no jogging
“addRoutingHalo” / “deleteRoutingHalo”
Tips: snap objects (region/guide/macro/blockage to instance grid or routing track)
Tips: “floorplan -> clear floorplan” = “deleteAllFPObjects” / “deleteSelectedFromFPlan”

instance group#

create instance group to group instances without changing the logic hierarchy for physical implementation
createInstGroup / addInstToInstGroup
OR createLogicHierarchy to change the netlist if preferred

auto finish floorplan#

“floorplan -> automatic floorplan -> finish floorplan”

save floorplan#

writeFPlanScript

How to reduce die size#

shape is important, considering routing layers are diff in horizontal and vertical directions
start from 70% utilization, then iteratively evaluate the timing/congestion results

Module 06: power plan#

What is power planning?#

create rings/strips
define global power/ground nets, as well as power structures

commands#

“power -> power plannning -> …” or addRing/addStripe/editPowerVia
- Full Geometry Checker (FGC) is enabled under 20nm process
“power -> connect global nets” or globalNetConnect to connect PG nets logically
- globalNetConnect VDD -type pgpin -pin VDD -all
- globalNetConnect VSS -type tielow
- ?shouldn’t this be a part of UPF’s function?

add rings#

for whole core or blocks or IO
advanced tab
- extend to re-use core ring for block rings
- add ring around cluster of selected blocks
  - addRing -type block_rings -around cluster/shared_cluster
- use wire groups, to avoid max width DRC

add stripes#

the concept of “set”
- ex. physically the power/ground wires are (VDD–VSS——VDD–VSS), then the set distance is from first VDD to next VDD
also have the option to connect to wire groups of the ring
advanced tab
- break strips at block ring: “omit stripes inside block rings”
- “merge with ring” to save resource by defining a threshold
- setAddStipeMode -orthogonal offset to control strips go beyond or within the edge of the block
- setAddStripMode -break_at blocks_without_same_net to disjoint stripes in different power domain

via gen#

for overlap area of strip/ring
shrink size of via to allow more routing resources for signal
“target penetration”: how long the target wire goes into the fat wire

Tips#

ignore DRC during early stage, to save run-time

Register-based SRAM Read Circuit RTL Example using generate

Wed, 18 Jan 2017 00:00:00 +0000

Some parameterized example RTL code for register-based SRAM read circuit using “generate” feature

parameter d = 32; // FIFO depth
parameter w = 64; // FIFO data bit-width

logic [w-1:0] mem [d-1:0]; // FIFO memory array
logic [d-1:0] rwl; // 1-hot read word line

// read circuit using "generate"
wire [w-1:0] word_or;
genvar width, depth;
generate
 for (width = 0; width < w; width++) begin: rbit
 wire [d-1:0] bit_or;
 for (depth = 0; depth < d; depth++) begin: rmux
 assign bit_or[depth] = mem[depth][width] & rwl[depth];
 end
 assign word_or[width] = |bit_or;
 end
endgenerate

reg [w-1:0] idout;
always @ (negedge CKB) begin
 idout <= word_or;
end

SystemVerilog for Design Note

Tue, 10 Jan 2017 00:00:00 +0000

This is my reading note of book “SystemVerilog for Design (2nd edition)". As a non-full-time RTL designer, it has opened my mind. But still, I’m sad about the antient tool that we are using to design hardware.

Chapter 2: SystemVerilog Declaration Spaces#

Package#

Verilog shortage: no global declaration
package ... endpackage
- share user-defined type definitions across multiple modules
- independent of modules
- parameters cannot be redefined
  - in package, parameter is similar to localparam, cos in module localparam cannot be directly redefined while instantiation
referencing
- :: the scope resolution operator
  - package_name::package_member
- use import to import package into current space
  - import package_name::package_member
    - TIPS: importing an enumerated type definition will not import the labels automatically
  - import package_name::*
    - what is used will be imported
- $unit declaration space
TIPS: synthesis guide
- tasks and functions must be automatic
  - storage for automatic task/function is allocated each time it’s called
- cannot use static variables, which are supposed to be shared by all instances

$unit: compilation-unit declarations#

declaration space outside of package/module/interface/program
- BUT it’s not global
if put variables and nets in $unit
- source code order can affect the usage of a declaration external to the module
each compilation has one $unit
- single-file compilation
- multiple-file compilation: source order is tricky
TIPS: coding guide
- DONOT make any declarations in $unit space, only import packages into $unit
- ILLEGAL to import the same package more than once into the same $unit
- NOTE: donot work for global variables, static task/function

// filename: def.pkg
`ifdef DEF_PKG
`define DEF_PKG

package def;
// ...
endpackage
`endif

// in every design or testbench file that need package "def"
`include "def.pkg"

identifier search rules

local
package
- named first
- * wildcard second
$unit
design hierarchy

TIPS: synthesis guide
- use packages instead of $unit
- external task/function must be automatic

Named/unnamed statement blocks#

local variables in named blocks can be accessed hierarchically
local variables in unnamed blocks (added in SV) has no hierarchical path
- protecting from external, cross-module referencing

Timing units and precision#

problem with Verilog’s timescale directive: file order dependent
SystemVerilog improvements
- time value with time units: 5ns, 3.2ps
  - NOTE: there is no space between number and unit
scope-level time units and precision: timeunit & timeprecision keywords
- must be immediately after module/interface/program declaration
search order

local
parent module/interface
timescale in effect while compilation
defined in $unit
simulator default

Chapter 3: SystemVerilog Literal Values and Built-in Data Types#

Literal value enhancement#

Verilog tricks to fill vector with all ones
- data = ~0; // one's complement
- data = -1; // two's complement
SystemVerilog: apostrophe(tick) ( ’ ) (Note: not back-tick ( ` ))
- data = '1; // all 1's
- data = 'z; // all z's

DEFINE enhancement#

String

// Verilog
`define print(v) $display("variable v = %h", v)
`print(data); // = $display("variable v = %h", data);

// SystemVerilog
`define print(v) $display(`"varaible v = %h`", v)
`print(data); // = $display("variable data = %h", data);

// SystemVerilog: escape with double `
`define print(v) $display(`"varaible `\`"v`\`" = %h`", v)
`print(data); // = $display("varaible \"data\" = %h", data);

Construct identifier names: double back-tick w/o space will separate names that will allow 2 or more names to be replaced and form a new name.

`define MY_NET(index) bit my_net``index``_bit;
`MY_NET(00) // = bit my_net00_bit;
`MY_NET(15) // = bit my_net15_bit;

Variables#

Type
- Net: “wire” keyword, only 4-state
- Variable: “var” keyword, most of the time it can be omitted
Data type: value system
- 2-state: “bit” keyword
- 4-state: “logic” keyword (to replace “reg” keyword)
Explicit & implicit (shit-hole of SystemVerilog)

// 4-state 8-bit varaible
logic [7:0] busA;
// to be explicitly
var logic [7:0] busA;

// 2-state 32-bit variable
bit [31:0] busB;
// to be explicitly
var bit[31:0] busB;

// 4-state 8-bit net
wire [7:0] busC;
// to be explicitly
wire logic [7:0] busC;

wire reg [31:0] busD; // ILLEGAL

Signed vs. Unsigned
- Concatenation automatic create unsigned result
- logic are unsigned by default
- int are signed by default
- syntax: <type> <signed/unsigned> <bit width> <name>;
TIPS: synthesis guide
- Because 2-state data types begins simulation with default 0 instead of X, if they are used in RTL may cause RTL behavior mismatch gate-level netlist. So they are mostly used in verification
- Converting from 4-state to 2-state, X and Z are mapped to 0
High level data type:
- 2-state data type: used for abstract model or DPI (Direct Programming Interface) to work with C/C++ model
  - byte: 8-bit
  - shortint: 16-bit
  - int: 32-bit
  - longint: 64-bit
- void: no storage
- shortreal: 32-bit single-precision = float in C, while real = double in C
- classes: not covered in this book
NOTE: Most signals can be declared as logic in RTL
- logic for single-driver
- wire for multi-driver logic (wand/wor)
Value drivers
- Any number of initial or always blocks
  - NOTE: it’s only for back-compatable with Verilog which is not really circuit behavior
- Single always_comb/always_ff/always_latch block
- Single assign statement
- Single module/primitive output/inout
Type casting
- Static casting (synthesizable)
  - Size casting: <size>'(<expression>)
    - ex. 16'(2) // 16-bit wide
  - Sign casting: <sign>'(<expression>)
    - ex. signed'({a, b}) // unsigned concatenation result to signed
  - Dynamic casting (has error check)
    - ex. cast(dest_var, source_exp);
Varaible initialization
- SystemVerilog in-line initialization is before time zero and does not cause a simulation event
- Testbench should initialize varaibles to their inactive state
Static and automatic variables
- static vs automatic
  - Storage
  - Automatic variables can be used for re-entrant tasks and recursive functions.
- Module level, all varaibles are static
- begin … end and fork … join blocks, tasks and functions, all storage defaults to static
- Automatic tasks and functions have all automatic storages
- Initialization
  - Static variables are only initialized once
  - Automatic variables are initialized each call

Constants#

Verilog
- parameter: can be redefined when instantiation
- specparam: can be redefined from SDF
- localparam: elaboration-time constant, cannot be directly redefined
SystemVerilog: C-like const keyword
- const int N = 5;

Chapter 4: SystemVerilog User-Defined and Enumerated#

`typedef` keyword#

Ex. typedef int unsigned uint;

Scan Chain Problem of Clock Generator Flip-Flops

Mon, 09 Jan 2017 00:00:00 +0000

As shown in the schematic, we have some clock divider that divide root clock by half. While in scan mode, these flip-flops will be bypassed and treated as normal flip-flop that need to be inserted into the scan chain along with leaf flip-flops. But due to the nature of clock tree, clock divider will be in the upper stream and will have a much smaller clock insertion delay. Then it will cause large hold time violation from clock generator flip-flops to normal leaf flip-flops, and these violations cannot be fixed easily.

My experience with custom digital design

Fri, 06 Jun 2014 00:00:00 +0000

Background#

This is the summary of my experience from project LBRAM in Marvell in the year of 2014.

The first thing: discuss timing/area/power SPEC’s in details#

Most of the time, because custom design takes lots of time, it often starts ahead of chips. At that time, the design SPEC’s, such as timing/area/power, are not clear. So try to discuss it with your supervisor or the project leader or your customer to define these SPEC’s even if they are not accurate. And do remember to write them down in some documents, so if they want to change the SPEC’s later, you can show them how absurd the idea is. ;-)

Survey of Low Power Design

Mon, 07 Sep 2009 00:00:00 +0000

从2017年初的观点来看，这篇报告的部分内容过时了，但是整体结构还是比较适合的。希望今年有时间能够出一版更新的版本。

低功耗设计的最根本驱动力是集成电路芯片的功耗随着工艺的进步不仅没有下降反而不断上涨。因为晶体管速度和集成度的上升速度超过了电路单次翻转所消耗能量的下降速度，所以单位面积芯片的功耗在迅速上升。而根据ITRS的预测，固定电源供电设备和移动设备中芯片的功耗发展趋势如图表 1所示。从中我们不难看出，各类芯片的各种功耗都在不断飞速上升，已经成为芯片设计者不容小觑的问题。

简介#

图表 1：芯片功耗的发展趋势：固定电源供电设备（左）和移动设备（右）

图表 2：不同工艺下芯片功耗发展趋势

同时，随着工艺的进步，提升晶体管速度的难度在不断增加，导致晶体管延时的下降幅度不断减小，如图表 2所示。因此为了继续提升电路的整体性能，芯片设计者不断引入新技术来弥补晶体管速度的不足。例如，使用低介电常数（Low-K）的电介质和低电阻率的金属线（铜金属线）。除此之外，许多其他技术的引入会进一步增加功耗，例如使用SOI（Silicon-on-Insulator）衬底材料、增加载流子迁移率（Strained Silicon）和提高电磁场强度（Overdrive技术）。这些新技术的引入不仅增加了单位面积内功耗的总量，还增加了漏电功耗在整体功耗中的比重，从而使得一些移动应用迫切需要进行低功耗设计。

时至今日，如何降低动态功耗是现在几乎所有IC设计者关注的焦点之一。对于使用电池供电的移动应用而言，降低芯片功耗能够延长产品的续航时间。这是一个非常具有诱惑力的特性。对于使用固定电源供电的应用而言，降低芯片功耗也能带来许多好处。例如，可以降低设备成本，因为能够使用更便宜的封装；能够达到更高的性能，因为芯片温度下降了。对于企业级数据存储和通信基站这样的系统而言，降低功耗更能够节约巨大的成本，因为可以使用更便宜的制冷系统。

功耗的基础概念#

功耗的分类#

图表 3：功耗的分类

如图表 3所示，我们将功耗分为动态功耗、短路功耗和漏电功耗。动态功耗为图中红色线条，当PMOS管开启时，为负载电容CL充电的电流引起的功耗。短路功耗为图中绿色线条，当输入信号发生翻转时，PMOS和NMOS会同时处于半开启状态，此时流经PMOS和NMOS的电流引起的功耗。漏电功耗为稳定状态下，MOS管的漏电涓电流（图中黄色线条）引起的功耗。

从公式中我们可以看出，动态功耗与短路功耗均与翻转概率、频率和电压成正比。

EDA工具功耗报告的分类#

在EDA工具的功耗报告中，功耗被分成三类：翻转功耗Switching，内部功耗Internal和漏电功耗Leakage。其中的漏电功耗很好理解，而翻转功耗与内部功耗与我们前面所提到的动态功耗和短路功耗稍有不同。

由于EDA流程是基于标准单元的设计方法，所以翻转功耗与内部功耗是针对标准单元来说的。我们知道每个电路节点都有寄生电容，因此也会有动态功耗。EDA工具的功耗报告中所提及的内部功耗就是当输入发生变化时，标准单元内部逻辑门的功耗损失，包括内部节点的动态功耗和内部MOS管的短路功耗。而翻转功耗指的是当输出发生变化时，标准单元对连线负载节点充电所引起的动态功耗。需要注意的是，单元A对单元B的输入端口PORT_IN进行充电所引起的动态功耗计算在内部功耗之列。

能量限制 vs. 功耗限制#

在低功耗设计领域有两种不同的应用需要区分清楚：能量限制的应用和功耗限制的应用。能量限制的应用有手机、笔记本、MP3等由电池供电的设备；功耗限制的应用有RFID等由电磁场供电的设备。

如图表 4所示，能量是由电流的面积积分决定的，所以能量限制的应用需要考虑的是一定时间范围内（通常是指工作和待机时间），其能量消耗（电流随时间的积分乘以电压）尽可能小。而峰值功耗则仅仅由电流的最大值决定，所以功耗限制的应用需要考虑的是瞬态电流（由于片上电容的存在，考虑一个微小时间片内的电流积分）小于电源能提供的最大电流。

图表 4：能量 vs. 功耗

这两种应用的功耗优化策略稍有不同，但是这样的不同之处是非常关键的。对于能量限制的应用而言，应该首先保证每次操作都是有效操作，并尽可能降低每次操作时消耗的能量。至于这些有效操作何时发生并不是非常重要。而对于功耗限制的应用而言，应该在时间上尽可能分散操作，不让芯片的峰值功耗超过供电源能提供的最大功耗值，但是刻意使得某一时刻功耗非常低也是没有意义的。

本文的结构#

在本文中，我们将首先讨论RTL级和门级（Gate-Level）下的一些优化策略。

能够归类于RTL级的低功耗技术比较少，因为在这一级大部分的优化都与具体的设计有直接的联系，所以能够提取出通用的方法并不多，主要是一些通用的在RTL编码中应该注意的问题。

现今的数字电路设计通常都是基于标准单元的设计方法，所以在门级我们主要关注一些可以借助EDA工具的优化策略和门单元的低功耗设计。

从前面的介绍中我们可以看到，动态功耗和短路功耗都与电压有直接的联系。所以降低电源电压是最直接也是最有效的低功耗设计手段。所以在接下来的一节我们将对这一类的设计方法进行讨论。有一些技术虽然还处于学术界的研究范畴，还没有在工业界大展拳脚，我们仍然需要对它们进行适当关注。

在现今的芯片设计中，时钟网络消耗了大量的功耗，必要对这一部分进行独立思考和优化。有不少低功耗技术的优化目标就是时钟网络。这部分内容我们将在之后进行介绍。

最后，我们将关心漏电功耗的优化策略，了解学术界和工业界对这部分功耗的优化成果。虽然在我们的应用中并不需要特别关注漏电功耗，但是这也是芯片功耗的一个重要组成部分，特别是对于手机这一类的手持移动设备而言更是如此。

RTL级优化策略#

RTL代码优化#

在RTL级，大部分对于低功耗优化策略都与实际的设计有密切的关系。需要RTL工程师对于代码综合以后的结果有清晰的认识。在这里我们将首先提出一些针对RTL代码的优化策略。虽然说某些设计精良的综合工具能够帮助我们实施某些优化，但是为了以防万一，也为了缩短综合工具的优化时间，我们应该在设计RTL代码时就将这些优化策略考虑进去。

提取公因子#

尽可能找出计算中重复使用的公因子进行重用，有的时候我们需要根据实际情况进行一些功能相等的转换。需要注意的是，综合工具对某些类型的公因子不敏感，所以我们应该在RTL设计中进行预处理。

提取公因子举例：能减少一个加法器

优化前

if (test)
 y0 = a + b;
else
 y1 = c - a - b;

优化后

assign t = a + b;
if (test)
 y0 = t;
else
 y1 = c - t;

资源重用#

通过代码优化将运算部件（例如关系运算、加减乘除等）进行重用。有的时候综合工具并不能很好的识别出需要做改进的地方。

Chisel3 Systolic Array Generator

Mon, 01 Jan 0001 00:00:00 +0000

#hardware #accelerator #chisel #open-source

I’ve tried to learn Chisel 5 years ago, but gave up and went back to SystemVerilog to design our RISC-V CPU + AI custom instructions from scratch. After 5 years, both Chisel and myself grow a lot, so I’m giving it another shot. This time, I found Chisel3’s documentation and tutorial is way better than 5 years ago. With numerous answers on Stack Overflow, LLVM’s CIRCT, Chisel simulator Treadle, and unit-test framework ChiselTest, it’s much easier to write and test Chisel/Scala.