Industry on When Moore's Law Ends

Hardware Security

Mon, 07 Jan 2019 00:00:00 +0000

Keynote panel on RISC-V Summit 2018: opportunities and challenges in security for open source hardware#

Complex systems tend to have bugs, so making it preparatory will make it more secure from attacks. But open source simple systems attract more eyes to review so that it becomes more and more secure over time.
Military and government customers want secret projects.
We need to change the way we design system
- Formal analysis
- More eyes on it, and keep things open
Weakness in RISC-V

RISC-V Summit 2018

Tue, 04 Dec 2018 00:00:00 +0000

My notes on RISC-V Summit 2018 at Santa Clara Conventional Center#

This year’s summit has many more participants than the last one, which means RISC-V is getting a lot of momentum around the world. Although most of the speeches are technology-detail-less propaganda thing, we still can find something useful out of it. And more importantly, talking to the engineers manning the booth is very interesting and information rich.

SiFive’s biz model#

Help customer to tape-out prototypes, and sell chips back to the customer.
- Fundamentally similar to old school design house
Front-end is a highly configurable design generator, with which customers can easily change the configuration and get the SoC RTL. Then they can drop-in their proprietary IP with TileLink interface.

SiFive’s Freedom Revolution platform#

SiFive acquired OpenSilicon, and it gets HBM2/Interlaken/… IPs, with their own 7-series CPU core (dual issue), they now can offer full SoC solution to custmers
Interlaken: chip-to-chip connection, 1.2Tbps, proprietary (not open source)

Hwacha v4#

Vector register file
- Different from new RISC-V vector ISA, it merges storage of low precision registers
Sequencer
- Systolic bank unit
  - Stall free, like TPU
VRU: vector runahead unit
- As I understand, it only prefetch the instruction, not the data. Actually the data part is more critical in prefetch
Polymorphic extension
- ? What?

platformIO.org#

Cloud, unified IDE for remote debug and CI
Free and open-source
Goes down to OpenOCD level, if we can make the hardware drives to support OpenOCD, then it can support it.

RENODE#

Simulator of RISC-V system
PolarFire SoC

David Patterson’s keynote speech#

Learn from the software side of progress
When Moore’s law stops, people catch up
- Apple A12 is better than Intel’s CPU in single thread performance
Security challenge nowadays is more and more serious
RISC-V committee: slower, but last longer
Open ISA vs. open hardware
TPU: software controlled memory (instead of cache)
Serverless computing
- Raise the level of abstraction
- Not x86 forever

Yunsup Lee’s keynote speech#

From customer: “we need more customization”
EDA on cloud: Cadence + MS Azure

Rob (NXP)‘s keynote speech#

Fragmentation is a big concern
VEGA board + PULP
- 2x PULP cores + 2x ARM cores
Foundries.io
- Software around RISC-V

AntMicro Keynote speech#

Several things are going too slow
- Linux-enabled cores
- Non-CPU IP is still hard
- Supply chain of making chips is painful
Solution: FPGA
LiteX: open platform for Linux and MicroSemi

SNUG Silicon Valley 2017 at Santa Clara Conventional Center

Sun, 30 Apr 2017 00:00:00 +0000

Day 1 Morning#

Paper from microsoft

Microsoft has a IC design team? Apparently it does.
Grey code: even when metastability happends, it falls to adjecent states, instead of unknow states, it’s acceptable in some cases.
Data bus bridge (DBB) for low data throughput
Async FIFO: more area, more complexity

Panel: synthesis into the future

The disruption in advanced nodes (10nm/7nm)
- Thermal: drives max freq; heating wires degreeds EM lifetime
- IoT: analog-digital co-design; physical/electical context-aware synthesis (the tool need to be aware of the block’s specific attributes, such as thermal/IR to avoid analog/digital interference. Ex: PLL cause high IR drop so it cannot be placed near some sensitive digital blocks)
- Power: low power is usually focused, but power density is more important. Thermal dissipasion is the key to successful product.
Context includes 2 different aspect
- Chip-level placement and interface
- Thermal dissipation
Accurate variation modeling is important for the digital
Blind clock gating for big blocks is not very good for IR drop, because it will create large power/ground noise. Instead, use smaller cores to go continuously is a better choice other than using large powerful cores working on and off.
My take-aways: future EDA will merge front-end and back-end. The flow will be unified, as well as the interface and engines. It will require engineers to know better for the whole flow. It fits my understanding of full stack engineer.

Day 1 Afternoon#

Paper from Broadcom about DSP ungrouping

Not interesting as expected.
Issue with auto ungrouping: design hierarchy change, or even port/logic change/moving
- constraint need to change (it seems Broadcom use hand written constraint file for synthesis and timing analysis, instead of dump out SDC from Synthesis tool to use it in STA)
- script need to change
- porting script from one design to another is difficult
Potential target to choose for ungrouping?
1. no ungroup at all vs. auto ungroup
2. analyze both timing reports to find out critical paths that improved after ungrouping
3. only ungroup the paths that improved
One take-away: they dump out timing paths into text files and do post-processing using Python. Another one is from my question, they use unified constraint files for both synthesis and STA, instead of write out SDC from synthesis tool and use it in STA. That actually make sense because unified constraint files are more understandable.

Configurable design using SystemVerilog

Virtual classes, parameters, interfaces and etc to make RTL design more configurable. The author did some research abour work-arounds and what is synthesizable with current DC and VCS.
Afterwards, I had a very interesting talk with the author and some other audiences. One important thing the others mentioned is that even 99% of the tools support one feature, and if the other 1% is not will kill the whole schedule. And they were beaten up a lot by other designers or front-back-end engineers because they use advanced coding techiques from SystemVerilog in their RTL. Some guy from Qualcomm mentioned that he was forbidden to use even parameters in his block. So it seems that there are not strong willing to switch from Verilog to SystemVerilog, especially from management level because nobody want to take risks in exchange of some configurability. That actually leads to my question to them that if anybody sees any performance improvements by using SystemVerilog. The author mentioned that using “for” loops instead of multiple “assign” will help the compiler to understand design intent and somehow improved the performance in one case.

Day 2 Morning#

Nanotime used in NVIDIA (Robert)

The presentation is from its memory team. The author mainly focused on the POCV features in Nanotime, and how to embedded ocv_sigma tables in liberty file from extract_model. And they did some correlation between POCV in Nanotime against Monte Carlo in HSPICE. The correlation is not very good at present time with the characterization script (to generate OCV parameter for each kind of transistors) provide by Synopsys. He also mentioned that they are going back to close the loop by feedback the correlation result into characterization script, hoping to improve the accruacy.
Transistor variation coefficient (characterization script from Synopsys)
- set_variation_parameters
- for every individual types of transistors (different parameters)
- transistor variation in stack series is different: more stack less variation
How to validate the path variation?
- Use SPICE Monte Carlo simulation after write_spice from Nanotime.
How to choose candidate for DDS?
- Critical paths
LVF tables (ocv_sigma) have delay/transition/setup/hold

Nanotime flow in Wave Computing (Roger Carpenter)

Product
- 16K instances of DPU
- Entire core is custom design
  - Network-on-chip, PCIe, DDR, HMC (Hybrid Memory Cube)
- Global async local sync design
Runtime issue? No.
Coverage report to define the completion of constraint coverage
Nanotime vs. write_spice
- TT 25c no SI: delta < 8%
This is very interesting for myself personally because they are using custom digital design approach to implement deep learning accelerators which can achieve 10GHZ (actually what I heard is 6.7GHz in 16nm). They used schematic and hand placment, used pulse latch + domino logic + global async local sync clocking scheme. They used to use spice to close timing on their DSP core (which has 16k instances overall) in 28nm but finally moved into Nanotime. It is a very interesting company. And amazing to hear that anybody is still using this “lost art” in real chip design.
Afterwards, we have several people gathering around to talk about this. A guy from Intel also mentioned that Intel themselves have moved away from custom design.

Deep learning and Siri by Alex Acero @ Apple

Thu, 23 Mar 2017 00:00:00 +0000

AI and ML#

Artificial intellegence vs human intellegence The imitation game, eugen Goosman passed the Turing Test, 2014 Alpha Go, deepmind 2015

Introduction to deep learning#

Improve on task T with respect to performance metric P based on experience E Perceptron learning (one layer NN): a(i) = a(i-1) + n * {target - output} * A(i) 1974 multi-ayer perceptron with backpropagation training deep learning is old tricks, more computing power, more data makes it possible and powerful Binary classification TouchID, speaker verification, face verification, emal spam, motion detection, credit card fraud N-ary classifiction MNIST (handwriting), speaker identification, word prediction (typing on iphone) Deep learning for speech (Deng, 2010)

Deep learning with GPUs in production

Tue, 21 Mar 2017 00:00:00 +0000

Start-up: python -> enterprise: C/Java/Scala, more engineers, faster Research: quick result and prototyping

GPU? Data movement between GPU and CPU is important

[ ] fast.ai: class (high school math)

infrastructure: spark/flink scheduler problem distributed file system

Problems to think about when running works on GPU clusters memory is relatively small throughput, jobs are more than matrix math resource provisioning: how many resource we need? GPU/CPU/RAM GPU allocation per job Python <-> Java overhead, defeats the points of GPUs

未来的AR应该是什么样子的？

Tue, 21 Feb 2017 00:00:00 +0000

今天去参加一个AI的meetup，碰到了一个连续创业者。他介绍了自己正在做的事情：“改变现有的输入方式，不应该是人给机器输入指令，而应该是机器预测人的需求并作出相应的动作。”，这才是机器的未来。同时他提到输出界面应该AR（增强现实）这种类型的，而不应该是一个显示屏幕。

Note of Deep learning for image and video processing tutorial

Sat, 21 Jan 2017 00:00:00 +0000

By Jon Shlens and George Toderici from Google Research @ 2017-01-20 Fri

History
- Convolutional NN: old tech, why suddenly it works?
  - Scale: 60M parameters
At least 60M +1 data point to fit these parameters
SIMD hardware (GPU)
- Domain transfer
  - Use trained CNN (with large data set) on some other applications with limited data set
CNN (convolutional neuron network)
- Toy model of a neuron
  - Sum over weighted input + nonlinear activation function to output
  - Very little relationship with real neuron
- Softmax classifier

智能用电的革命

Sat, 21 Jan 2017 00:00:00 +0000

一场涉及普通消费者的智能用电革命正在悄然发生。加州政府近年来努力推动这项能源节约革命，在近三年来取得了快速的进步，得到了能源公司和电器制造商的广泛支持。

Prosumer的概念#

普通家庭以往是以单一的电力消费者出现的。但是近年来由于太阳能发电设备的推广力度不断加大，得到了大量消费者的欢迎和支持，催生了prosumer的概念，即producer + consumer。通过政府大力支持的贷款在自家屋顶安装太阳能板，并将发出的电力上网卖给电力公司，同时获得最低单价的用电费用。我的同事中就有不少安装了，或者正在考虑安装这样的设备，表明这样的project即使对于普通的三口或四口之家都是有利可图的。

智能用电#

电网消费有峰有谷，这样的波动由于各个小区域的消费习惯、天气变化等密切相关，而且往往变化迅速，即以分钟为单位反复变化。但是电网负载波动对于电网设备而言是有害的，所以电力公司有非常强烈的意愿通过某些技术手段来消弭这样的波动。这样就提出了“智能用电”的概念，也就是通过对普通的电器进行联网和远程自动控制，来调节小区域内部的用电波动。这样不仅能降低电网设备的负载，也能够有效利用能源，所以对于电力公司和政府决策者而言都是大有益处的。对于普通消费者而言，积极参与“智能用电”项目能够获得的利益来自于电力公司和政府政策补贴。

举例说明，热水器和烘干机之类的设备是耗电量大户，但是往往对于时效性要求不是很高。如果能够加入特定的芯片进行联网控制其功率，取代恒定的大功率输出，就能够起到平衡电网负载波动的左右。代价可能仅仅是将原有的工作时间延长一些而已。再者就是目前越来越普及的电动车。对于普通使用者而言，充电时间远远大于使用时间。如果在足够的充电时间内自动选择电网负载最低的时段进行充电就能够获得最低的电价。

另外的小事#

加州一些城市的商业区或者大型shopping center开始自行安装一些电动车充电桩。这些充电桩在非高峰期（周末或者节假日）是免费的。这样就吸引一些开电动车的顾客来充电和消费。

Bluetooth hub from Cassia Networks

Tue, 27 Sep 2016 00:00:00 +0000

今天的CES meetup是一个清华85级的学长来宣传他们自己公司的bluetooth hub，Cassia Networks。如果简单从名字上来看并没有什么高端的感觉，毕竟bluetooth和hub两个东西都不是什么稀奇的东西。但是它获得了2016年CES大会最佳产品奖项，可不是浪得虚名。

它解决了bluetooth的痛点，而且是用现有的商业化芯片，在系统集成和固件上下功夫，通过对协议的深刻理解，得到了超出世人的性能：不需要对master和slave有任何的额外要求就能达到300+米的传输距离（相对于普通的10+米极限），能够穿过三堵墙，可以连接多个master和slave，并转发数据（虽然现有的Bluetooth标准并不支持路由功能）。而且，他们还在此基础上开发了开放的SDK，能够对接其他的软硬件厂商，并由此展现出在多个应用场景下的广泛应用前景。这款产品的厉害之处就在于它极大的拓展了Bluetooth在IoT领域的应用范围，甚至给予了Bluetooth这个标准更大的想象空间。

个人的思考：

坚持在一个领域深入挖掘，即使是已经有非常成熟的标准、广泛应用的技术和芯片产品，也能够厚积薄发取得突破甚至带来该领域的应用革新。
坚持使用商业化芯片，因为已有的芯片功能其实能够在大部分时间充分满足应用需要，不必动辄开发一款ASIC来解决“+10%”的问题。

Observation of IC Industory consolidation of future application

Sat, 06 Aug 2016 00:00:00 +0000

Recent consolidation progress is going so crazy, mostly because of the IC industry is becoming less and less profitable in every individual application fields. My perspective is that this is not just a consolidation of business itself, but a huge change of IC industry business model. There won’t be so many application fields that needs different IC chips, no matter it’s analog or digital. In analog world, more and more functionality will be replaced with digital as long as it can. It’s inevitable just like in digital world, more and more functionality will be replaced by software, as long as it can.

Optical Interconnection in Google Data Centers

Tue, 11 Aug 2015 00:00:00 +0000

今天的Meetup主要讲的是Google的Data Center中optical interconnection的应用。

Presentation之后问了一个问题：Google的Data Center里面是否HDD正在被SSD取代？回答是，并没有，因为虽然SSD在读写速度上有明显的优势，但是由于存储容量的性价比非常低，所以仅是作为缓存使用。也就是说在HDD和DRAM之间再加一层SSD来提升存取速度。看来老板Sehat的FLC其实是基于市场选择而做出的理智判断（甚至不能说是预测，因为已经成为工业现实）。而且如果enterprise如果能够迅速跟上以弥补mobile市场的萎缩，Marvell在硬盘市场应该还能继续赚取利润。

Follow-up @ 2019-02-11: Sehat已经被挤出了公司，FLC项目也随之夭折。当时做这个项目的Marvell的同事们出去搞了一个自己的公司，拿到了Sehat的投资，正在如火如荼的做这个项目。时至今日，SSD仍然没有把HDD完全取代，但是根据Marvell最近的财务状况，HDD的市场萎缩的很厉害。

IDF (Intel Developer Forum) 2015 San Francisco, Moscone Center

Wed, 01 Jul 2015 00:00:00 +0000

Intel IoT platform
- Intel IoT Platform
  - Sensors and things
    - Arduino
  - Gateway
    - transfer data between different types of networks
    - some data processing as well
    - moving quickly: different types of data
    - flexibility is important for scalability
    - PMA: protocol mapper and adapter (UPAL)
  - Security
    - not only data, but also physical security
  - data storage
    - physically distributed
    - depend on the data types, and there are so many of them
    - different users use the same data in many different ways
      - provide different sets of APIs at business level
- Real world IoT challenges
  - 3 major areas
    - connected things and devices
    - intelligence and the edge
    - turn data in to insight
  - different applications
    - cities: e.g. drain block sensor network
      - connected things and devices
        
        regulatory:delay tolerance
        
        harsh conditions: device robust
        
        long distance: zigbee is not useful anymore
        
        security
      - intelligence ant ht edge
        
        low power
        
        OOB ML
        
        sensor fusion
      - turn data into insight
        
        diverse ecosystem
        
        multiuse data
        
        data ownership
    - smart grid
      - high freq
      - extreme reliabliity
        
        challenging environment
      - manageablity
      - security
      - demand response
      - actuation
      - data privacy
      - data volumen
      - public/private
    - industrial
      - legacy integration
        
        very old implementation
      - multi-protocols
      - zero downtime
      - security
        
        multi million equipments
      - bespoke feeds
      - data translation
      - ML customisation
      - enterprise/network
      - integration
      - business rules
- Smart cities
  - future of flood management
    - approach
      - work with cicies
        
        city managers have the requirements and most of the experience
      - prototype
        
        Intel IoT gateway: extend the life of equipment by make use of old equipments that already exists
        
        custom flood detecting sensor
        
        software and simulation in matlab (openTSDB)
      - deploy and iterate
        
        deploy the implementation is time consuming and fruastrating for engineers
        
        iteration is important for this kind of experiment projects
- Smart grids: enernet
  - put sensors in families and get their energy usage profiles
  - and make use of these data
- Data center
  - to increase visibility to resource usage
Data analytics and machine learning Intel fellow
- what is machine learning
  - a computer program learns, if tis performance improves with experience, Tom Mitchell
  - 3 types
    - superviesed learning: large amount of learning data, and people label data out
    - unsupervised learning: make inferences without labeled data
    - reinforcement learning: act in an env to maximize reward, real learning process
- why now, tech is decades old, why sudden hot now
  - machine makes real decisions now
  - big opportunity: extract value from data. things x data = value
- relationship to other workloads
  - similar to high performance computing, and showing more and more similarities
  - traditional: inside-out process
  - emerging: outside-in process, from data to knowledge
  - machine learning combines both of these 2 processes
  - models
    - algorithms
      - database primitives
      - graph algo
      - machine learning
      - numeric cmputing
- intel architecture-specific optimization
  - key msg
    - machine learning is the most significant emergin algorithm class today
    - publicly available code is highly inefficent in terms of its parallelism-awareness
    - code modernization: signle-node or distributed
    - enhance both processor and tool chain
  - how intel tools accelerate machine learning
  - why deep learning is so exciting
    - shallow learning: one layer
    - deep network layers can apply to parallelism
    - go deeper in the layers, the system learn and got more clear idea of the target
  - Intel Xeon + FPGA (from Altera)
Internet of things software standards unscrambled
- Creating a Model
- Simple Layer Model
  - application and service <-> data & control points
  - profiles, data & resource models
    - how IoT devices are represetned to app and servcies
    - how app and servcie interact vith the represetnations
  - comms protocols <->
    - high level protocols, multi-layers
  - transports <->
    - physical layers and low level protocols
- standards for locao IP, internet and cloud
  - local to local via internet?
  - cloud to cloud connect?
- deliverables
  - traditional standard
    - specification
    - certification
  - code
    - for developers, open source projects, de facto standard
- IP
  - trademark
  - copyright
  - patent
- standard
  - intel is behind both IIC & OIC
  - open source is changing the formation of standard. so intel is contributing open source code
- Future?
  - never be one standard to rule them all
  - recurring themes
    - consistency
    - low power and constrained services
    - security
      - machine to machine communication
      - different user/admin will have different level of access
  - IP, REST-based
  - cooperation
    - interoperation
    - collaboration
    - consolidation
Realsense
- 3D camera and develope kit
IoT (windriver & VxWorks)
- 2015 is the peak of inflated expectations
- tech wave: 1B+ desktop internet » 10B+ mobile device » 50B+ IoT
- 2 business interests
  - optimization
    - new efficientcies: more data of things that cannot collectable before
  - transformation
    - new revenue streams
    - transitionsing business models
    - positive shifts in value creation and value capture
- how to get started with IoT
  - platform, integrited from left (things) to right (cloud)
    - things side
      - embedded system
    - gateway
    - cloud side
      - network
      - data center
      - cloud analytics
  - secure from end to end: edge-to-enterprise

DAC 2015

Fri, 19 Jun 2015 00:00:00 +0000

汽车设计正在成为EDA公司的讨论热点。我个人觉得ANSYS应该算是其中翘楚，因为各种物理模拟器和散热模拟器是他们的传统强项。而诸如Synospsys和Mentor这样的软件厂商就更多的focus在电子系统上，硬件软件全部都有。
From Mindy: EDA厂商每年都要收购大量的小公司来保证自己的创造力。
ARM推出了专门针对Bluetooth 4.0的IP库和demo
有一家叫做flexlogic的公司，专门做FPGA阵列的IP，用于在普通的ASIC芯片上embed FPGA模块。但是这个模块的规模一般不会太大。跟他们现场的工程师聊天发现，他们和Marvell做SSD的Engling已经有合作了，用FPGA做在调试接口上，以少量的PIN来支持多种不同的调试协议。想法还是挺有创意的。

ISSCC 2015 evening session - Moore's Law challenges below 10nm

Mon, 23 Feb 2015 00:00:00 +0000

Bohr: moore’s law for 50 years
- $mm^2$ is increasing since 130nm
- heterogeneous intergration: 3D chip is not a replacement of moore’s law (quite opposite with Sehat)
- refocus on general purpose design
Hill: 21 century computer architecture
- 21stcentruryarchitecturewhitepaper.pdf - instruction set is not going to be untouchable anymore - energy first - parallelism - specialization - cross-layout design - cross-cutting: break current layers with new interfaces - BREAK LAYERS - software bloat - PHP is 50x slower than BLAC - 3D stack - how to address thermal problem? the power is reduced by 3D stacking
1.3 Madden