Blogs

Recently, I’m trying out different HDL generator languages and tools, because Chisel is used heavily inside SiFive, and they have developed amount of IPs including very complicated CPUs, and a very well maintained community (mainly students from Berkeley) Many other IP companies are using their type of HDL generator to generate RTL Such as ARM and Cadence. ARM’s CPU is delivered as a very well parameterized Verilog file along with a set of scripts that can take your configuration file can generate RTL/testbench/IPXACT/… accordingly in less than a minute.

Cache coherence between CPUs are most explained in textbooks, but IO coherence is not well understood. Recently I’m involved in architecture discussion about IO coherence, and found this paper, “Maintaining I/O Data Coherence in Embedded Multicore Systems” by Thomas B. Berg 2009, very useful coming to explain what is IO coherence and how to implement it in embedded system. I/O Coherence Producer-consumer model Most mechanisms for passing data between IO device and CPU, either CPU -> IO or IO -> CPU, use the classic producer-cosumer model.

FANG Frame Problem statement & background Assumption Based on best info Non-goals Something NOT trying to solve Goals Something trying to solve Avoid Too long of framing, not history lession Facts are not assumptions Goals/non-goals are for “solution” not “discussion” Best Practice FANG-only doc, stop short of proposals By taking away potential solutions helps converge on FANG first before solution It takes aways the bias on potential solutions

From Cloning yourself isn’t an option by Camille Fournier Everyone wants to have clones to help them with certain work. But additive is linear improvements while multiplier is trying to achieve exponential improvements Tech skills are foundamental, BUT Availability bias: the more skilled a person is on a dimension, the more important they consider that activity to be. Be too afaid of being detached from tech is over exaggerated.

From Self-evaluation and improvement in engineering leadership How manage a remote/distributed teams? Communication is the key. TODO: setup regular communication channel. Knowing the ppl you are working with, the methods of communication they prefer. Peer support for growing as a leader? It’s a lonely road, unlike engineering, there is not much sharing between peers. And different managers may have totally different problems.

AMBA (ARM Advanced Microcontroller Bus Architecture) 1. AXI AXI protocol is a point-to-point protocol So no matter what the network channels really use, as long as its ports comply AXI protocol, IP can be connected to them Main features Separate read/write channels Improve bandwidth Multiple outstanding requests No strict timing relationship between address and data phases Unaligned data transfer Out-of-order transaction completion Implicitly incremental address for burst transfer Transfer vs transaction Transfer is a handshake: valid/ready Transaction is composed of multiple transfers Active transaction: already started but not finished.

Simple Sequential Execution Model After optimization, the result should be exactly the same with “simple sequential execution model”. Optimization: Instruction Fetching Fetch multiple instructions from memory Branch Predictive fetch and execution Branch caches Return stack The “link register” value is pushed into the stack, and used/popped when return E.g. 4 entries of return stack, but my call stack is 5, then miss will happend. Then what to do?

ARM online training note 1. Introduction What is an architecture? Instruction set Exception model Memory model Debug ARMv8 AArch32 vs AArch64 AArch32: backward compatible to ARMv7 AArch64: fixed 32-bit instruction, new exception model, 64-bit virtual address Priviledge and security model 4-level of privilege EL0 < EL1 < EL2 < EL3, larger the higher privilege 2 security modes Mixture of AArch32 and AArch64 Only 64-bit OS can host a mix of 32-bit and 64-bit apps 32-bit app can only be on lower EL level 2.

Reference Interrupt Categorization Hardware vs. Software Hardware: usually caused by peripheral or other processors IRQ: maskable interrupt NMI: non-maskable interrupt For highest priority tasks, like times, especially wathdog timers Wathdog timer: a timer has to be reset by software on purpose periodically, otherwise it means the software has gone into some hanging situation and will trigger watchdog routine to recover or reboot. IPI: inter-processor interrupt Software: caused by exception or special instructions that used to implement system calls Interrupt vs inter-process communication signal Interrupt: mediated by the processor (hardware); handled by the kernel Signal: mediated by the kernel (through systeam call); handled by processes Such as: SIGSEGV, SIGBUS, SIGILL, SIGFPE Precise vs imprecise interrupt Precise interrupts has PC and other architecture states are saved, so after interrupt handler is done the current process can resume All instructions before the time point have fully executed, and no instructions beyond has been executed (or they are killed) Triggering methods Physical interrupt Level-triggered vs.

Typical usage go to some directory use short alias > pwd /home/jw > go prj0 cd /work/projects/design/master-branch/ > pwd /work/projects/design/master-branch/ run a serial of commands use short alias > run vnc ssh -L 5901:remote-internal-server-name:5901 jw@remote-gateway-ip vncviewer remote-internal-server-name Search available alias Here . dot is used to replace * star because zsh will try to expand * by default. > go prj0 > go p. prj0 > run vnc Auto-correction shortcut.py uses difflib.