arch

Register renaming To eliminate the false and output data dependency by adding extra physical registers more than architectural registers. Read-after-write (RAW) is true data dependency Write-after-write (WAW) is output data dependency Write-after-read (WAR) is false data dependency Superscalar Dynamically issue multiple instructions in each cycle to increase IPC. Normally need multi-port register files and ALU to avoid structural hazard. Can be in-order or out-of-order Re-order buffer For out-of-order execution CPU architecture, results are put into re-order buffer waiting for commit.