I’m a chip designer working on the digital side. I’ve got experience with
- CPU/SoC architecture and design, especially RISC-V open ISA
- IC design/verification with Verilog/SystemVerilog/SystemC
- Low power design and optimization
- ASIC design flow, including front-end, back-end and power sign-off
- Semi-custom design flow, including transistor timing analysis and SPICE simulation
Currently my interests are
- Harware and software co-design
- SoC generator
- Machine learning accelerator
If you share the same interest and want a discussion, please send me a message on LinkedIn
Work expereince
1-stop solution: Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit (https://www.xilinx.com/products/boards-and-kits/zcu111.html)
Features: XCZU28DR-2FFVG1517E: high-end RFSoC 12-bit 4GSPS ADC x8, 14-bit 6.5GSPS DAC x8 (all RFSoC has the same type of ADC/DAC, no higher speed ones) Pros: 1-stop with everything we need for bench-top demo Cons: expensive $9K, need secondary solution for backup; overkill for second step product FMC daughter board with high-speed ADC
Price of GCP Persistance Disk Can be used to put all the data/eda/os on it.
Price (per month) Price (per GB per month) SSD 50GB $8.50 $0.17 SSD 1TB $174.08 $0.17 HDD 50GB $2.00 $0.04 HDD 200GB $8.00 $0.04 HDD 1TB $39.76 $0.04 Snapshot 50GB $1.30 $0.026 Always on instance (24x7) Can be used as working machine (support VNC) and NFS server
Dockerfile FROMubuntu:16.04COPY ./boot.sh /tmpCOPY ./hello.sh /tmpRUN /bin/bash /tmp/boot.shRUN /bin/bash /tmp/hello.shboot.sh apt-get update; apt-get install -y make autoconf g++ flex bison wget cd /tmp wget https://www.veripool.org/ftp/verilator-4.004.tgz tar xf verilator*.tgz cd verilator* ./configure make # this step will take sometime make install hello.sh cd /tmp/verilator* cd ./example/tracing_c make # it will print out some log, and after finish it will generate a directory in the same directory named "logs" who needs to be saved after container exit Docker how-to notes create a docker image from Dockerfile docker build -t "$(name):$(tag)" .
If your design needs to switch from one clock source to another, there is high possibility of harmful clock glitches while switching. Normally you need to stop this clock during the switching process, but what if you design relies on non-stop clock? Here is the circuit proven to work on silicon.
Techniques to make clock switching glitch free
We used it in our 28nm TSMC HPC+ chip, after we carefully simulated it with HSPICE.
The course is on Coursera
understanding design patterns what? well-known solutions for recurring problems why? don’t reinvent wheels reuse best practices characteristics language neutral dynamic incomplete by design to promote customization types creational structual behavioral OOP (object-oriented programming) design pattern relies on OOP attributes + methods inheritence & polymorphism pattern context participants and their rols quality attributes: nonfunctional requirements forces: various factors or trade-offs to consider consequences: side effects by decision makers pattern language name context problem solution related patterns creational patterns factory create and return object on the fly flexibility of adding new classes problem uncertainties in types of objects runtime decision of types of objects abstract facotry a factory dynamically uses different factories to create objects on the fly problem create a family of related objects at runtime concepts abstract factory concrete factory (the real factory used at runtime) singleton only one object from a class problem cache information shared by multiple objects
Scala introduction course on LinkedIn. Not very useful, if not using it in real project.
introduction short for Scalable language object-oriented + functional programming everything is object including numbers and functions does not include primitive data types can pass/assign function: functional programming seamless compatible with Java runs on JVM, compile to JVM reuse Java libraries and types can call any Java code REPL interactive shell read, eval, print, loop syntax define: var (variable) vs val (value) var defines variables that can be changed but cannot change from one data type to another, ex.
The following is my notes of GENUS training course on Cadence’s training module
Module 03: genus fundamentals common UI vs legacy mode unified commands with Tempus common us: set_db & get_db legacy mode: set_attribute & get_attribute .synth_init file: setup info, auto load when start legacy UI, can be skipped with -no_custom command line option explore design hier in legacy UI virtual directory structure /: root dir designs top_module instances_hier: current module’s hier instances instances_seq: current module’s sequential instances instances_cmb: current module’s combinational instancs libraries hdl_libraries flows use find to locate objects ex.
Day 1 Morning Paper from microsoft Microsoft has a IC design team? Apparently it does. Grey code: even when metastability happends, it falls to adjecent states, instead of unknow states, it’s acceptable in some cases. Data bus bridge (DBB) for low data throughput Async FIFO: more area, more complexity Panel: synthesis into the future The disruption in advanced nodes (10nm/7nm) Thermal: drives max freq; heating wires degreeds EM lifetime IoT: analog-digital co-design; physical/electical context-aware synthesis (the tool need to be aware of the block’s specific attributes, such as thermal/IR to avoid analog/digital interference.
To start gnome-terminal on WSL (Windows Subsystem for Linux) After upgrade to Windows 10 Creators Update, reinstall WSL will have Ubuntu 16.04.2 LTS on Windows.
To reinstall WSL you should do:
> lxrun /uninstall /full
> lxrun /install
Then you will see
> lsb_release -a
No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 16.04.2 LTS
Release: 16.04
Codename: xenial
Some X11 apps like xclocks works fine with Xming, but “gnome-terminal” still have some problem.
In general, things like Anaconda Server are designed to make this sort of workflow easier.
Some suggested workarounds:
Reproduce your install on another machine with internet (save conda list –export to a file and conda install –file). Then use conda update on that machine to generate and download the packages. One tip that could be helpful is if you take several conda packages and tar them up into a flat tarball you can use conda to install that tarball and it will install all the packages.