Project

Latch-based RAM semi-custom macro design change This project was for some specific customer. We already have HPM version design from previous project, although there were still some improvements we’d like to do. In LP version latch-based RAM, we wanted to use new floorplan which has smaller width and larger height. This would help the SoC team to achieve easier floorplan and better routability. And with old floorplan, the internal routing was the limitation, especially in horizontal direction.

Ultra-high-frequency RFID design and low power optimization Our team designed a UHF RFID product with TSMC 90nm process. My major responsibility was to reduce the power consumption to compete with world leading products. The whole RFID chip consumed about 10uW peak power. After ran power estimation and determined that the most energy consumed part was clock tree, due to input capacitance of flip-flops. I designed a new flip-flop with ultra-low input capacitance, which as only 4 clock transistors, using semi-dynamic technique.

High-Speed full-custom register file design From Mar. 2004 to Jan. 2006 This whole project’s purpose is to design high speed multi-synchronious read and write port register file to meet the ultra high frequency and bandwidth requirement of a 1GHz 4-issue 64-bit general purpose RISC CPU. We need to implement a SRAM with independent 8 read ports and 4 write ports with read latency less than 500ps. Our solution is to use 2 SRAM with identical data content.