Ultra-high-frequency RFID design and low power optimization

Our team designed a UHF RFID product with TSMC 90nm process. My major responsibility was to reduce the power consumption to compete with world leading products. The whole RFID chip consumed about 10uW peak power.

After ran power estimation and determined that the most energy consumed part was clock tree, due to input capacitance of flip-flops. I designed a new flip-flop with ultra-low input capacitance, which as only 4 clock transistors, using semi-dynamic technique. From post-layout simulation, the peak power is reduced by 10% to 15%, approximating the leading product on market. And this solution can be easily transferred to other chips and projects.

To adapt this new DFF into design flow, I designed a set of Python scripts to (1) generate stimulus and netlist for HSPICE simulation; (2) gather data from HSPICE results, calculate and create Liberty timing file, because of lacking of automation tool.

I also designed a BIST block for DFF function and delay test. And the DFF is verified by tape-out.