RISC-V Architecture Training

General software stack Embedded system software stack What is newlib? https://en.wikipedia.org/wiki/Newlib C standard library implementation for embedded system GCC port for non-Linux embedded system When lacking of full-blown OS, how to make a system call and how to use devices Newlib code size will signaficant larger than Linux code size, because it includes the system calls that is already embedded inside Linux. What is cross-compile? Cross-compiler

Custom instruction The most attractive feature of RISC-V Extensibility Differentiation Software hardware co-design Domain-specific applications   Example Integer MAC (multiplication and accumulation) for matrix operation Multiple load/store fusion for smaller code footprint Customized vector operations tailored for your application Custom instruction / Difficulties Most difficult thing is NOT in hardware, but in compiler How to let compiler understand your intention and generate corresponding instructions For example, automatic vectorization is difficult with vector/SIMD instructions The compiler has to understand the for loop, as well as the implemention details @DEMO: new MAC instruction MAC = multiplication and accumulation c += a * b RD = RD + RS1 * RS2 Most common operations in matrix multiplication How to handle Overflow?

Freedom IDE Different targets Targets Comments qemu-sifive-e31 QEMU emulator for 32-bit E31 CPU qemu-sifive-s51 QEMU emulator for 64-bit S51 CPU freedom-e310-arty Arty FPGA platfrom sifive-hifive-unleashed SiFive’s HiFive Unleased board that support Linux sifive-hifive1 SiFive’s HiFive1 board sifive-hifive1-revb SiFive’s HiFive1-RevB board Emulate on QEMU QEMU is a full system emulator Translate target instruction to host instruction Only functional (not trace accurate) but really fast It’s good for software development, not for hardware debugging @DEMO: qemu-sifive-e31-sifive-welcome QEMU emulator version 3.

PK and FESVRV PK (proxy kernel) & FESVR (front-end server) For debug and system bring up PK is an abstraction of kernel that provides system services through FESVR running on host PK is running on target CPU, while FESVR is running on host computer PK and FESVR / code example printf in modified version of spike *# Original spike > cd ~/riscv-training/lab/22-lab.system-call > spike .

QEMU QEMU is a binary translating emulator On-the-fly, translate RISC-V instruction to host CPU instruction (e.g. x86) Functional, not accurate; but really fast Good for software debugging, not for hardware debuggin Type Example Performance Functional QEMU 100 million to >1 billion instructions per second Trace-accurate Spike 10 to 100 million instructions per second Cycle-accurate Verilator/rocket-chip 10 to 100 thousand instructions per second RISC-V boards virt - priv v1.

Install VMWare Player Create Ubuntu 16.04 from provided virtual machine Username = riscv Password = r5rocks Install Freedom Studio from SiFive https://www.sifive.com/boards They have Windows / Mac OS / Linux versions. @LAB Path in LAB VM /opt/FreedomStudio-2019-08-2-lin64 Setup shell environment export SIFIVE=/opt/FreedomStudio-2019-08-2-lin64/SiFive export RISCV=${SIFIVE}/riscv64-unknown-elf-gcc-8.3.0-2019.08.0 export QEMU=${SIFIVE}/riscv-qemu-4.1.0-2019.08.0 export PATH=${RISCV}/bin:${QEMU}/bin:${PATH} @LAB Above setup has been added into .bashrc @LAB: Hello world cd ~/riscv-training/lab/20-lab.setup-env make Here is the log: make hello.elf SRC_TYPE=c make[1]: Entering directory '/mnt/hgfs/riscv-training/lab/20-lab.

riscv-tests https://github.com/riscv/ Unit tests based on assembly Basic functionality of each RISC-V instructions and features defined in the spec Very good staring point to find basic implementation issues Software BIST (built-in self test) Compare architecture states with expected results Issue pass/fail signal to host machine Official compliance tests riscv-tests / TVM (test virtual machine) Because RISC-V is very scalable, so it has many variants E.

RISC-V SPEC https://riscv.org/specifications (official version v1.10 while version v2.0 under ratification) https://github.com/riscv/riscv-isa-manual (source code)  User-level ISA (unpriviledged) All the basic instructions, and extensions Memory model Priviledged ISA Priviledge level: M (machine), H (hypervisor), S (supervisor), U (user) CSR (control status register) Virtual-memory system Debug & Trace First impression: ISA subsets RISC-V is a family of ISAs Divided into several subsets: I, M, A, F, D, C, …

Computer architecture basics  Pipeline / Parallelism / Cache Three ultimate mechanisms to imporve performance/power Computer architecture basics / pipeline IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). Computer architecture basics / pipeline @DEMO Pipeline simulator: https://github.com/mortbopet/Ripes Computer architecture basics / pipeline Motivation Most of the work cannot be done at the same time. To use the logic more efficiently Less work per stage, higher clock frequency Brings in problems: hazards Data hazard Dependency mv x1, x2 add x4, x1, x3 sd x4, 0(x5) Control hazard Jump and branch addi x1, x1, 1 subi x2, x1, 100 bnez x2, 0(x3) .

What is RocketChip generator? RISC-V SoC generator from UC Berekeley Based on Chisel Highly parameterized Cache configs Num of cores Type of cores (Rocket, BOOM, w/ FPU, RoCC accelerator) Num of ports (memory, system, peripheral) What is RocketChip generator? / Setup Clone GIT repo git clone --recursive https://github.com/chipsalliance/rocket-chip.git export RISCV=/opt/riscv/rv64gc # need to use matching RISC-V toolchain export PATH=${RISCV}/bin;${PATH} Prerequisites Because RocketChip is using Chisel (a variant of Scala, based on Java), so we need to install JDK before using RocketChip generator.