RISC-V Architecture Training

What is ISA? Contract between software and hardware. What is RISC? Reduced instruction set computer Small set of simple/general instructions + load/store architecture Optimize hardware to be simple and faster Software-centric design: rely on compiler + software CISC RISC Emphasis on hardware Emphasis on software Includes multi-clock complex instructions Single-clock, reduced instruction only Memory-to-memory: “LOAD” and “STORE” incorporated in instructions Register to register: “LOAD” and “STORE” are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers E.

Privileged architecture Purpose of privileged architecture To manage and protect shared resources Memory, IO devices, even cores Also needs to decouple implementation details Handle unimplemented operations: software emulation Handle async events (interrupts): IO, timer, software Hypervisor support: 2-level address translation Therefore, we have 4 privilege modes: U, S, H, M PMP/PMA (physical memory protection/attributes) Virtual memory Interrupts and exceptions And a bunch of CSRs to serve these functionality Privileged architecture / software stack layers 4 different kinds of platforms Platforms Modes Trust Memory protection Embedded w/o protection (most MCUs) M All Non Embedded w/ protection (RTOS scenario) M+U Application Physical memory protection OS capable (Linux, and etc.

Schedule 2-day x 8-hour Step-by-step Lecture + demo + lab Schedule / Day 1 morning Schedule and self-introduction [Lecture] Introduction of RISC-V open ISA History and current status of ecosystem [Lecture] RISC-V ISA: unprivileged spec Basic RISC-V ISA: key concepts [Lab] Setup lab env Quick introduction of lab env used in this course ==== Lunch break ==== Schedule / Day 1 afternnon [Demo] Compile assembly code and simulate on SPIKE

– Uncore CPU core is fun, but uncore is the real work. Uncore / components Cache (already discussed) Interrupt controller Network Fabric Debug Interrupt recap 3 types of interrupts External: peripheral devices Software: inter-processor interrupt Timer: timely schedule tasks PLIC (platform level interrupt controller) For external interrupts Aggregation of multiple external interrupts Provide enable/priority CLINT (core level interruptor) For software & timer interrupts Provide memory-mapped software/timer interrupt CSRs PLIC (platform-level interrupt controller) MSI vs.